Vertical Ferroelectric HfO<inf>2</inf> FET based on 3-D NAND Architecture: Towards Dense Low-Power Memory

Karine Florent, Milan Pešić, A. Subirats, +10

Non-volatile MemoryEngineeringEmerging Memory TechnologyFerroelectric Random-access Memory3D Memory +15

First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

S. Subramanian, M. Reza Hosseini, T. Chiarella, +29

EngineeringN14 PlatformInterconnect (Integrated Circuits)Complementary FetPhysical Design (Electronics) +14

InGaAs Gate-All-Around Nanowire Devices on 300mm Si Substrates

Niamh Waldron, Clément Merckling, Lieve Teugels, +7

IEEE Electron Device Letters

SemiconductorsNanowire DevicesElectrical EngineeringSemiconductor TechnologyEngineering +12

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

Niamh Waldron, Clément Merckling, Weiming Guo, +21

EngineeringOptoelectronic DevicesIntegrated CircuitsSilicon On InsulatorSemiconductor Device +17

First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

E. Capogreco, Liesbeth Witters, Hiroaki Arimura, +21

IEEE Transactions on Electron Devices

Semiconductor TechnologyElectrical EngineeringEngineeringRf SemiconductorPhysics +11

Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

Hans Mertens, R. Ritzenthaler, Hiroaki Arimura, +18

EngineeringIntegrated CircuitsSilicon On InsulatorSemiconductor DeviceSemiconductors +14

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

Liesbeth Witters, Hiroaki Arimura, Farid Sebaai, +26

IEEE Transactions on Electron Devices

SemiconductorsSemiconductor TechnologyElectrical EngineeringEngineeringNanoelectronics +10

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning

Hans Mertens, Maryam Hosseini, T. Chiarella, +37

Electrical EngineeringEngineeringVlsi DesignMicrofabricationNanotechnology +12

Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS

A. Veloso, L.-Å. Ragnarsson, M. J. Cho, +29

Symposium on VLSI Technology

Low-power ElectronicsMaterials ScienceElectrical EngineeringEngineeringVlsi Design +12

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

Niamh Waldron, Sonja Sioncke, J. Franco, +21

Semiconductor TechnologyElectrical EngineeringWafer Scale ProcessingIii-v Gate-all-around DevicesEngineering +11