C.P. Tsao

A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications

Shien-Yang Wu, M.C. Chiang, C.Y. Lin et al. · 2022 International Electron Devices Meeting (IEDM) · 2022 · 56 citations

Engineering, Electrical Engineering, High-performance Computing +17

32nm gate-first high-k/metal-gate technology for high performance low power applications

C.H. Diaz, Kenichi Gotō, H.T. Huang et al. · 2008 · 36 citations

Engineering, Electrical Engineering, Low-power Design +10

Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond

Chih‐Hao Chang, Vincent S. Chang, K.H. Pan et al. · 2022 International Electron Devices Meeting (IEDM) · 2022 · 31 citations

Engineering, Computer Engineering, Electrical Engineering +16

Applying dynamic voltage stressing to reduce early failure rate

C.P. Tsao, R.Y. Shiue, Chen-Ching Ting et al. · 2002 · 12 citations

Engineering, Computer Engineering, Electrical Engineering +14