J. Mitros

High-voltage drain extended MOS transistors for 0.18-μm logic CMOS process

J. Mitros, Chin-Yu Tsai, H. Shichijo et al. · IEEE Transactions on Electron Devices · 2001 · 91 citations

Low-power Electronics, Electrical Engineering, High-voltage Drain +10

Thickness dependence of stress-induced leakage currents in silicon oxide

E.F. Runnion, S.M. Gladstone, R.S. Scott et al. · IEEE Transactions on Electron Devices · 1997 · 90 citations

Trap-assisted Tunneling, Non-volatile Memory, Electrical Engineering +14

16-60 V rated LDMOS show advanced performance in a 0.72 μm evolution BiCMOS power technology

Chin-Yu Tsai, T. Efland, S. Pendharkar et al. · 2002 · 28 citations

Low-power Electronics, Wide-bandgap Semiconductor, Electrical Engineering +15

Limitations on oxide thicknesses in flash EEPROM applications

E.F. Runnion, S.M. Gladstone, R.S. Scott et al. · 1996 · 27 citations

Materials Engineering, Non-volatile Memory, Electrical Engineering +14

A performance comparison between new reduced surface drain "RSD" LDMOS and RESURF and conventional planar power devices rated at 20 V

T. Efland, Chin-Yu Tsai, J. Erdeljac et al. · 2002 · 18 citations

Low-power Electronics, Surface Drain, Electrical Engineering +13