S. Manakli - Concepedia

Author

S. Manakli

STMicroelectronics (France)

Also Known As

Christophe Soonekindt, Manakli, S., S. Manakli, Serdar Manakli

Publications

309

Citations

H-Index

Concepts

All Affiliations

STMicroelectronics (France)Commissariat à l'Énergie Atomique et aux Énergies Alternatives Laboratoire d'Électronique des Technologies de l'Information CEA Grenoble STMicroelectronics (Czechia)

About

S. Manakli is an author at STMicroelectronics (France) specializing in microelectronics, engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	7	7	165
2	Computer Engineering	5	5	133
3	Electrical Engineering	5	5	138
4	Applied Physics	4	4	105
5	Social Sciences	1	1	11

S. Manakli

Publications

207

Citations

H-Index

Page 1

	Year	Citations
Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm<sup>2</sup> 6T-SRAM bitcell C. Fenouillet-Béranger, J. Todeschini, Jean-Christophe Le-Denmat, Pmos TransistorsSemiconductor TechnologyElectrical EngineeringEngineeringNanoelectronics	2007	61
A conventional 45nm CMOS node low-cost platform for general purpose and low power applications F. Arnaud, M.T. Basso, D. Sotta,	2004	42
A Cost-Effective Low Power Platform for the 45-nm Technology Node E. Josse, S. Parihar, Olivier Callen, EngineeringVlsi DesignIntegrated Circuits45-Nm Technology NodePower Electronics	2006	33
32nm node BEOL integration with an extreme low-k porous SiOCH dielectric k=2.3 K. Hamioud, V. Arnal, A. Farcy, Microelectronic Engineering Materials ScienceElectrical EngineeringEngineeringNanoelectronicsApplied Physics	2009	16
Transitioning of direct e-beam write technology from research and development into production flow L. Pain, B. Icard, S. Manakli, Microelectronic Engineering Industrial DesignEngineeringMicrofabricationIndustrial EngineeringFabrication Technique	2006	16
0.248μm/sup 2/ and 0.334μm/sup 2/ conventional bulk 6T-SRAM bit -cells for 45nm node low cost - general purpose applications F. Arnaud, C. Boccaccio, F. Salvetti, Electrical EngineeringNode Low CostEngineeringVlsi DesignAdvanced Packaging (Semiconductors)	2005	14
Electron beam direct write lithography flexibility for ASIC manufacturing: an opportunity for cost reduction (Keynote Paper) L. Pain, M. Jurdit, J. Todeschini, Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE EngineeringElectron-beam LithographyComputer ArchitectureCost ReductionAsic Manufacturing	2005	14
MAGIC: a European program to push the insertion of maskless lithography L. Pain, B. Icard, S. Tedesco, Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE European ProgramEngineeringElectron-beam LithographyMicroscopyTarget Fabrication	2008	11

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