S. Manakli

Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm² 6T-SRAM bitcell

C. Fenouillet-Béranger, J. Todeschini, Jean-Christophe Le-Denmat et al. · 2007 · 61 citations

Pmos Transistors, Semiconductor Technology, Electrical Engineering +13

A conventional 45nm CMOS node low-cost platform for general purpose and low power applications

F. Arnaud, M.T. Basso, D. Sotta et al. · 2004 · 42 citations

A Cost-Effective Low Power Platform for the 45-nm Technology Node

E. Josse, S. Parihar, Olivier Callen et al. · 2006 · 33 citations

Engineering, Vlsi Design, Integrated Circuits +19

32nm node BEOL integration with an extreme low-k porous SiOCH dielectric k=2.3

K. Hamioud, V. Arnal, A. Farcy et al. · Microelectronic Engineering · 2009 · 16 citations

Materials Science, Electrical Engineering, Engineering +6

Transitioning of direct e-beam write technology from research and development into production flow

L. Pain, B. Icard, S. Manakli et al. · Microelectronic Engineering · 2006 · 16 citations

Industrial Design, Engineering, Microfabrication +10