L. Pain

Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm² 6T-SRAM bitcell

C. Fenouillet-Béranger, J. Todeschini, Jean-Christophe Le-Denmat et al. · 2007 · 61 citations

Pmos Transistors, Semiconductor Technology, Electrical Engineering +13

A Cost-Effective Low Power Platform for the 45-nm Technology Node

E. Josse, S. Parihar, Olivier Callen et al. · 2006 · 33 citations

Engineering, Vlsi Design, Integrated Circuits +19

A functional 0.69 μm/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform

F. Arnaud, F. Salvetti, D. Lenoble et al. · 2004 · 30 citations

Low Power, Electrical Engineering, Engineering +14

5 kV multielectron beam lithography: MAPPER tool and resist process characterization

David del Rio, C. Constancias, M. Elena Martín et al. · Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena · 2010 · 27 citations

Electrical Engineering, Wafer Scale Processing, Engineering +14

Low cost 65nm CMOS platform for Low Power & General Purpose applications

F. Arnaud, B. Duriez, B. Tavel et al. · 2004 · 24 citations

Low-power Electronics, Low Power, Electrical Engineering +10