L. Pain - Concepedia

Author

L. Pain

Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Also Known As

L Pain, L. F. Pain, L. Pain, L., Pain, Pain, L.

Publications

431

Citations

H-Index

Concepts

All Affiliations

Commissariat à l'Énergie Atomique et aux Énergies Alternatives Laboratoire d'Électronique des Technologies de l'Information STMicroelectronics (France)CEA Grenoble Institut polytechnique de Grenoble

About

L. Pain is an author at Commissariat à l'Énergie Atomique et aux Énergies Alternatives specializing in microelectronics, engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	11	12	285
2	Applied Physics	8	8	201
3	Computer Engineering	7	7	187
4	Social Sciences	1	1	11
5	Chemistry	1	1	15

L. Pain

Publications

285

Citations

H-Index

Page 1

	Year	Citations
Fully-depleted SOI technology using high-k and single-metal gate for 32 nm node LSTP applications featuring 0.179 μm<sup>2</sup> 6T-SRAM bitcell C. Fenouillet-Béranger, J. Todeschini, Jean-Christophe Le-Denmat, Pmos TransistorsSemiconductor TechnologyElectrical EngineeringEngineeringNanoelectronics	2007	61
A Cost-Effective Low Power Platform for the 45-nm Technology Node E. Josse, S. Parihar, Olivier Callen, EngineeringVlsi DesignIntegrated Circuits45-Nm Technology NodePower Electronics	2006	33
A functional 0.69 μm/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform F. Arnaud, F. Salvetti, D. Lenoble, Low PowerElectrical EngineeringEngineeringVlsi DesignBeam Lithography	2004	30
5 kV multielectron beam lithography: MAPPER tool and resist process characterization David del Rio, C. Constancias, M. Elena Martín, Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena Electrical EngineeringWafer Scale ProcessingEngineeringElectron-beam LithographyBeam Lithography	2010	27
Low cost 65nm CMOS platform for Low Power &amp; General Purpose applications F. Arnaud, B. Duriez, B. Tavel, Low-power ElectronicsLow PowerElectrical EngineeringAnalog Transistor ParametersVlsi Design	2004	24
Pattern density multiplication by direct self assembly of block copolymers: toward 300mm CMOS requirements Raluca Tiron, Xavier Chevalier, S. Gaugiran, Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE EngineeringPattern TransferIntegrated CircuitsCmos RequirementsPattern Density Multiplication	2012	24
Study on line edge roughness for electron beam acceleration voltages from 50to5kV David del Rio, C. Constancias, Mazen Saied, Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena Electrical EngineeringLer DependenceEngineeringResistorElectron-beam Lithography	2009	16
Transitioning of direct e-beam write technology from research and development into production flow L. Pain, B. Icard, S. Manakli, Microelectronic Engineering Industrial DesignEngineeringMicrofabricationIndustrial EngineeringFabrication Technique	2006	16
Resolution limit of negative tone chemically amplified resist used for hybrid lithography: Influence of the molecular weight L. Pain, Craig Higgins, B. Scarfoglière, Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena EngineeringElectron-beam LithographyResolution LimitChemistryWafer Scale Processing	2000	15
0.248μm/sup 2/ and 0.334μm/sup 2/ conventional bulk 6T-SRAM bit -cells for 45nm node low cost - general purpose applications F. Arnaud, C. Boccaccio, F. Salvetti, Electrical EngineeringNode Low CostEngineeringVlsi DesignAdvanced Packaging (Semiconductors)	2005	14

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