C.H. Chen - Concepedia

Author

C.H. Chen

Taiwan Semiconductor Manufacturing Company (Taiwan)

Also Known As

C. H. Chen, C.H. Chen, C.h. Chen, Chuanjie Chen

Publications

302

Citations

H-Index

Concepts

All Affiliations

Taiwan Semiconductor Manufacturing Company (Taiwan)

About

C.H. Chen is an author at Taiwan Semiconductor Manufacturing Company (Taiwan) specializing in electrical engineering, microelectronics, and engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	7	7	206
2	Electrical Engineering	7	7	206
3	Computer Engineering	6	6	189
4	Computer Architecture	3	3	110
5	Applied Physics	2	2	55

C.H. Chen

Publications

251

Citations

H-Index

Page 1

	Year	Citations
A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications Shien-Yang Wu, M.C. Chiang, C.Y. Lin, 2022 International Electron Devices Meeting (IEDM) Low-power ElectronicsElectrical EngineeringCmos Platform TechnologyEngineeringVlsi Design	2022	49
A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process Shien-Yang Wu, J.J. Liaw, Chih‐Yung Lin, Symposium on VLSI Technology Low-power ElectronicsMb Sram Test-chipElectrical EngineeringEngineeringVlsi Design	2006	42
32nm gate-first high-k/metal-gate technology for high performance low power applications C.H. Diaz, Kenichi Gotō, H.T. Huang, Low-power ElectronicsElectrical EngineeringSemiconductor DeviceEngineeringVlsi Design	2008	36
A 90 nm CMOS MS/RF based foundry SOC technology comprising superb 185 GHz f/sub T/ RFMOS and versatile, high-Q passive components for cost/performance optimization C.H. Chen, Chia-He Chang, C.P. Chao, Foundry Soc TechnologyPassive ElementsFoundry 90EngineeringSuperb 185	2004	29
A 32nm CMOS Low Power SoC Platform Technology for Foundry Applications with Functional High Density SRAM Shien-Yang Wu, Chung-Cheng Chou, C.Y. Lin, Low-power ElectronicsSystem On ChipElectrical EngineeringFunctional 2MbEngineering	2007	19
Investigation of Sensitivity Improvement on Passive Voltage Contrast for Defect Isolation Jon C. Lee, C.H. Chen, David Su, Microelectronics Reliability Electrical EngineeringEngineeringSensitivity ImprovementDefect IsolationPassive Voltage Contrast	2002	17
First Demonstration of Monolithic CFET Inverter at 48nm Gate Pitch Toward Future Logic Technology Scaling Siyong Liao, Wei-Xiang You, Ting Wu,	2024	15
Silicon integrated high performance inductors in a 0.18 μm CMOS technology for MMIC Heng-Ming Hsu, Jiong-Guang Su, Shyh-Chyi Wong, Electrical EngineeringEngineeringVlsi DesignEddy Current LossAdvanced Packaging (Semiconductors)	2002	14
Direct plating of Cu on ALD TaN for 45nm-node Cu BEOL metallization Chun-Hsing Shih, H.W. Su, C.J. Lin,	2005	10
Enabling Multiple-Vt Device Scaling for CMOS Technology beyond 7nm Node Vincent S. Chang, S.H. Wang, Jen-Hsiang Lu,	2020	10

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