Hybrid-FE-Layer FeFET With High Linearity and Endurance Toward On-Chip CIM by Array Demonstration

Abstract

Analog weight cells based on ferroelectric field-effect transistors (FeFETs) are promising for fast and energy efficient compute-in-memory (CIM) accelerators, yet their on- chip training is hindered by the limited linearity and endurance. To address this critical issue, we introduced a novel FeFET design featuring a hybrid ferroelectric layer of Hf0.5Zr0.5O2 and Hf0.95Al0.05O2 with Al2O3 interlayers. The proposed FeFET achieves a high linearity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha _{\text {p}}= -0.48$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\alpha _{\text {d}}= -1.73$ </tex-math></inline-formula> , good endurance of over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{9}}$ </tex-math></inline-formula> cycles, and a fast switching speed of ~50 ns. The mechanism of such improvement was probed carefully by comparison with control devices. The benefit of device optimization was experimentally demonstrated by performing an on- chip training task on a 1T NOR array, and the system-level benchmarking of the CIM accelerator based on our FeFET shows an overall superior performance. This work contributes to the development of FeFETs for on- chip neuromorphic hardware.