Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node

Abstract

This paper evaluates the impact of backside power delivery on the physical implementation of a commercial 64-bit high-performance block from ARM™ at the A14 node. A backside BEOL, including TSV connections, is proposed and calibrated using TCAD and experimental data. The developed stack is modeled in a commercial cell-level parasitic extraction tool to enable its use during place and route. The same benchmark is physically implemented using imec’s own A14 PDK. The backside PDN enables frequency improvements from 2% to 6% compared to frontside PDN, stemming from a core area reduction from 8% to 16%. These results are obtained without negatively impacting the total power and simultaneously limiting dynamic IR drop below 35mV. Furthermore, different TSV options have been studied to potentially boost the IR drop gains up to 23%.