Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders

Abstract

In this article, we present the design of approximate adders which provide dynamic runtime configurability between exact and approximate modes at the circuit level. We propose the single exact single approximate (SESA) adders that allow for fine grain configurability between exact and approximate modes. We also propose the single exact dual approximate (SEDA) adder that allows for coarse grain configurability between exact and approximate modes. Unlike SESA adders, the SEDA adder allows for two approximate computations at a time. Both the SESA and SEDA adders have a maximum bounded error. We implemented SESA and SEDA adders using UMC 28-nm technology node and evaluated them using the Cadence virtuoso tool. On average, SESA and SEDA adders consume 40% and 51% lesser energy when compared with the exact mirror adder when used in approximate mode. We have evaluated our result on image addition and image enhancement using 16-bit SESA and SEDA adders. We also evaluated 32-bit SESA and SEDA adders on the Moby benchmarks to highlight their use in approximate processors.