Effect of Floating Gate Insertion on the Analog States of Ferroelectric Field-Effect Transistors

Abstract

In this work, we propose a structural approach to mitigate device-to-device variation and performance degradation of ferroelectric (FE) field-effect transistors (FeFETs) due to the inhomogeneity of FE and dielectric (DE) phases of the FE layer. We found that by inserting a floating gate below the FE layer, the polarization effect of FE grains is equalized, thus suppressing the formation of an undesired current percolation path through the channel of the FeFET. This also results in a wider memory window and improved device variation, which ultimately improves the accuracy of in-memory computing. We believe that the proposed approach could be an important strategy enabling reliable and unified operation of FeFETs with the scaling of device.