A transparent virtual channel power gating method for on-chip network routers

A 5-GHz Mesh Interconnect for a Teraflops Processor

Yatin Hoskote, Sriram Vangal, A. Singh et al. · IEEE Micro · 2007 · 531 citations

Engineering, Computer Engineering, Computer Science +17

Asia and South Pacific Design Automation Conference 2010

2009 · 103 citations

Architecture, Design, Systems Engineering +10

Proceedings of the 2002 international symposium on Low power electronics and design

Vivek De, M.J. Irwin, Ingrid Verbauwhede et al. · 2002 · 73 citations

Engineering, Computer Engineering, Electrical Engineering +13

On-chip networks

Natalie Enright Jerger, Tushar Krishna, Li-Shiuan Peh · 2017 · 40 citations

Engineering, Computer Engineering, Computer Science +17

Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs

Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2011 · 38 citations

Engineering, Computer Engineering, Computer Science +17