2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022 · 36 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsMicrofabricationSemiconductor DevicesDevice ScalingIntegrated Circuit DesignVery-large-scale Integration Layout3D Integrated Circuits3D Nand ArchitectureMemory ScalingThree-dimensional Device ScalingThree-dimensional Integrated Circuit LayoutThree-dimensional IntegrationThree-dimensional MemoryYield Enhancement
Xtacking® architecture in 3D NAND flash expands the capability to achieve faster I/O speed and higher bit density. In Xtacking® architecture, independent processing of array and CMOS wafers facilitates innovations in both process technologies and design architectures. While 3D monolithic + heterogeneous integration poses substantial challenges, advanced topography optimization and wafer stress management techniques are developed to achieve highly reliable array and CMOS technologies with mature yield. The innovative Xtacking® architecture unleashes scaling potential for 3D NAND, and paves the way for future applications such as integrated SSD and in-memory computing.
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