2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · 2022 · 23 citations · 6 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsMicroelectronicsSemiconductor DevicesFerroelectric MaterialsMetal-oxide-semiconductor Field-effect TransistorsNanoelectronicsSemiconductor Device MaterialsSemiconductor PhysicsSemiconductor ReliabilityData RetentionDead ZonesFerroelectric Field-effect TransistorsFerroelectric SemiconductorsGate-all-around TransistorsMemory Window OptimizationNonvolatile MemoryNonvolatile Memory Materials
After 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> high endurance cycles with memory window (MW) =0.9 V is achieved for the 3D gate-all-around (GAA) nanosheet (NS) ferroelectric field-effect transistor (FeFET) based on double-HZO; the aim is to homogenize the corner field and mitigate dead zones. The interlayer Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> or TiN in the double-HZO exhibits MW enhancement or low access voltage, respectively. The proposed MFMFS GAA-FeFET demonstrates a low V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P/E</inf> = ±3.5 V (±2.3 MV/cm), large MW = 1.3 V, >10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> robust endurance cycles, and stable storage with data retention of >2×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s; therefore, physical dimension scaling of the embedded nonvolatile memory (eNVM) is feasible for future generations.
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