Investigation on Package Warpage and Reliability of the large size 2.5D Molded Interposer on Substrate (MIoS) Package

Abstract

2.5D silicon interposer integration package technology has been developed for high-end applications such as AI, datacenter, server, etc. In order to achieve higher performance, the types and number of integrated chips are gradually increasing. The package size is also increasing due to more number of chips to be integrated. As the package size increases, various technical challenges are accompanied by such as molded chip warpage, package level reliability or package warpage. In the previous study, we introduced a 2.5D package structure called Molded Interposer on Substrate (MIoS) which is composed of 2-logic and 8-HBM devices on 2800mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> size Si interposer. The package body size of 8-HBM MIoS package is 85x85mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . In this study, package warpage and reliability of large size package were investigated. Package warpage is caused by the CTE mismatch between organic substrate and molded interposer chip which is composed of Si devices. To compensate the package warpage induced by the CTE mismatch, a stiffener structure was attached. The warpage shape caused by CTE mismatch was investigated, and stiffener structure, stiffener material properties and adhesive material properties were studied to effectively compensate for the package warpage. The effect of each parameter on the package warpage was investigated through experiments and package warpage expectation model was developed. Also the package level reliability verification was performed for various structures controlling the package warpage. Through this study, package warpage control technology of large size 2.5D package with various sizes and configurations was achieved.