Reducing transistor count in clocked standard cells with ambipolar double-gate FETs

Abstract

This paper presents a set of circuit design approaches to achieve clocked standard logic cell functions with ambipolar double-gate devices such as the Double Gate Carbon Nanotube FET (DG-CNTFET). The cells presented in this work use the infield controllability of the device to reduce transistor count over conventional standard cells by only requiring n+1 transistors (where n is the fan-in), and achieve improved time delay by a factor of 2 for comparable power consumption.