Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis

Abstract

The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect Transistors (CNFETs) into limelight. Among the several design aspects necessary for today's grail in CNFET technology, achieving functional immunity to Carbon Nanotube (CNT) manufacturing issues (such as mispositioned CNTs and metallic CNTs) is of paramount importance. In this work we present a new design technique to build compact layouts while ensuring 100% functional immunity to mispositioned CNTs. Then, as second contribution of this work, we have developed a CNFET Design Kit (DK) to realize a complete design flow from logic-to-GDSII traversing the conventional CMOS design flow. This flow enables a framework that allows accurate comparison between CMOS and CNFET-based circuits. This paper also presents simulation results to illustrate such analysis, namely, a CNFET-based inverter can achieve gains, with respect to the Energy-Delay Product (EDP) metric, of more than 4× in delay, 2× in energy/cycle and significant area savings (more than 30%) when compared to a corresponding CMOS inverter benchmarked with an industrial 65nm technology.