Energy-delay Optimization
Energy-Delay Optimization is a systematic design methodology in subthreshold circuit design that minimizes the trade-off between energy consumption and signal propagation delay by jointly optimizing circuit parameters under performance constraints.
237
Publications
10.5K
Citations
672
Authors
204
Institutions
Publications per year
2017–2026
49
Parents
237
Ultralow-Power Design in Near-Threshold Region
Dejan Marković, C.C. Wang, Louis P. Alarcón et al. · Proceedings of the IEEE · 2010 · 365 citations
Engineering, Computer Engineering, Electrical Engineering +17
Energy-delay tradeoffs in smartphone applications
Moo-Ryong Ra, Jeongyeup Paek, Abhishek Sharma et al. · 2010 · 251 citations
1–5 of 237
672
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7
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1–5 of 672
204
University of California, Berkeley
Berkeley, United States
16 h-index
52 publications
4.7K citations
Georgia Institute of Technology
Atlanta, United States
11 h-index
36 publications
1.1K citations
Stanford University
Stanford, United States
11 h-index
28 publications
2.1K citations
Intel (United States)
Santa Clara, United States
11 h-index
22 publications
1K citations
University of Southern California
Los Angeles, United States
10 h-index
27 publications
2.8K citations
University of Illinois Urbana-Champaign
Urbana, United States
10 h-index
27 publications
1.3K citations
The University of Texas at Austin
Austin, United States
9 h-index
20 publications
728 citations

Pennsylvania State University
State College, United States
9 h-index
32 publications
1.6K citations
1–8 of 204
21 publications · 1.2K citations
17
h-index
8 publications · 1K citations
8
h-index
6 publications · 108 citations
6
h-index
5 publications · 141 citations
5
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5 publications · 243 citations
5
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1–5