A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region

TLDR

The model serves as a starting point toward a complete CNFET-device model that incorporates additional device/circuit-level non‑idealities and multiple CNTs reported by Deng and Wong. The paper presents a circuit-compatible compact model for the intrinsic channel region of MOSFET-like single-walled carbon-nanotube field‑effect transistors. The model is valid for a wide range of chiralities, diameters, and both metallic and semiconducting CNT channels; it incorporates quantum confinement, phonon scattering, and screening by parallel CNTs; a complete transcapacitance network is implemented for compatibility with digital and analog applications; and it is implemented in HSPICE. The model predicts a 13‑fold CV/I improvement for an intrinsic CNFET with a (19,0) CNT compared to a bulk n‑type MOSFET at the 32‑nm node.

Abstract

This paper presents a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field-effect transistors (CNFETs). This model is valid for CNFET with a wide range of chiralities and diameters and for CNFET with either metallic or semiconducting carbon-nanotube (CNT) conducting channel. The modeled nonidealities include the quantum confinement effects on both circumferential and axial directions, the acoustical/optical phonon scattering in the channel region, and the screening effect by the parallel CNTs for CNFET with multiple CNTs. In order to be compatible with both large-(digital) and small-signal (analog) applications, a complete transcapacitance network is implemented to deliver the real-time dynamic response. This model is implemented with an HSPICE. Using this model, we project a 13 times CV/I improvement of the intrinsic CNFET with (19, 0) CNT over the bulk n-type MOSFET at the 32-nm node. The model described in this paper serves as a starting point toward the complete CNFET-device model incorporating the additional device/circuit-level non-idealities and multiple CNTs reported in the paper of Deng and Wong.