A 64 b microprocessor with multimedia support

Abstract

A quad-issue microprocessor chip implements a 64 b architecture extension to a popular 32 b RISC instruction set. Additional instructions and dedicated hardware provide up to 10/spl times/ speed-up of image processing and rendering algorithms, including video compression/decompression and texture-mapped 3D triangles. The chip contains 5.2M transistors on a 17.7/spl times/17.8 mm/sup 2/ die in 0.5 /spl mu/m CMOS with 4 metal layers. The package is a 620-pin plastic BGA with 187 power and ground pins. Operating at 167 MHz, it dissipates less than 30 W from a 3.3 V supply.