A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAM

Abstract

A 512kb CMOS ECL SRAM with 2ns cycle and 4ns access for fully-random read/write operations uses a 0.8μm CMOS technology having a 0.5μm L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff"</sub> The 2ns cycle time is obtained through more aggressive use of pipelining than previously reported. The pipelining is transparent to the user.