Effect of Surface Texture on Pinhole Formation in SiO<i>_x</i>-Based Passivated Contacts for High-Performance Silicon Solar Cells

Abstract

High-efficiency silicon solar cells rely on some form of passivating contact structure to reduce recombination losses at the crystalline silicon surface and losses at the metal/Si contact interface. One such structure is polycrystalline silicon (poly-Si) on oxide, where heavily doped poly-Si is deposited on a SiO<i>_x</i> layer grown directly on the crystalline silicon (c-Si) wafer. Depending on the thickness of the SiO<i>_x</i> layer, the charge carriers can cross this layer by tunneling (<2 nm SiO<i>_x</i> thickness) or by direct conduction through disruptions in the SiO<i>_x</i>, often referred to as pinholes, in thicker SiO<i>_x</i> layers (>2 nm). In this work, we study structures with tunneling- or pinhole-like SiO<i>_x</i> contacts grown on pyramidally textured c-Si wafers and expose variations in the SiO<i>_x</i> layer properties related to surface morphology using electron-beam-induced current (EBIC) imaging. Using EBIC, we identify and mark regions with potential pinholes in the SiO<i>_x</i> layer. We further perform high-resolution transmission electron microscopy on the same areas, thus allowing us to directly correlate locally enhanced carrier collection with variations in the structure of the SiO<i>_x</i> layer. Our results show that the pinholes in the SiO<i>_x</i> layer preferentially form in different locations based on the annealing conditions used to form the device. With greater understanding of these processes and by controlling the surface texture geometry, there is potential to control the size and spatial distribution of oxide disruptions in silicon solar cells with poly-Si on oxide-type contacts; usually, this is a random phenomenon on polished or planar surfaces. Such control will enable us to consistently produce high-efficiency devices with low recombination currents and low junction resistances using this contact structure.