Gallium Nitride and Silicon Transistors on 300 mm Silicon Wafers Enabled by 3-D Monolithic Heterogeneous Integration

Abstract

We demonstrate industry's first 300 mm GaN transistor technology and 3-D monolithic heterogeneous integration with Si transistors, enabled by 300 mm GaN metal-organic chemical vapor deposition (MOCVD) epitaxy and 300 mm 3-D layer transfer. The 300 mm GaN technology is a high-k dielectric enhancement-mode GaN nMOS transistor technology on Si(111) substrate. It is capable of excellent characteristics and figure-of-merits (FOM) for realizing energy-efficient, compact power-delivery and RF front-end components such as power-amplifiers, low-noise amplifiers, and RF-switches. Our GaN nMOS transistors show e-mode operation with: 1) high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D,max</sub> = 1.5 mA/μm; 2) low R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> of 610 Ω - μm (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 50 nm); 3) low I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> of 100 pA/μm (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 180 nm), which are significant improvements over GaN HEMT; 4) excellent RF performance: f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> = 190 GHz, f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MAX</sub> = 300 GHz, power-added efficiency (PAE) = 56% (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 50 nm) at mmwave frequency 28 GHz, and PAE = 77% at 5 GHz (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 180 nm), significantly better than industry-standard GaAs and Si RF transistors; 5) good RF-switch FOM, R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> = 110 fs; and 6) low noise figure, NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> = 1.36 dB (f = 28 GHz) and 0.4 dB (f = 5 GHz), all at SoC-compatible voltages. We further demonstrate GaN transistor innovations all integrated on 300 mm Si(111) wafer, including depletion-mode GaN nMOS transistor with high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> = 1.8 mA/μm; GaN Schottky gate transistor producing high saturated power of 20 dBm (80μm width) with peak PAE = 57% at 28 GHz; low leakage compact cascode and multigate GaN transistors; and GaN Schottky diodes with ultralow C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> for electrostatic discharge (ESD) protection. The layer-transferred Si transistors, monolithically stacked on top of the GaN transistors by 300 mm 3-D layer transfer, show high drive current performance: 1.0 mA/μm (Si nMOS) and 0.5 mA/μm (Si pMOS). Such a monolithic 3-D Monolithic integration of GaN and Si transistors enables full integration of energy-efficient, truly compact power delivery and RF solutions with CMOS digital signal processing, logic computation and control, memory, and analog circuitries.