A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM

Abstract

In Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM), the most commonly used timing scheme for conventional Voltage-mode Sense Amplifier (VSA) is the global activated timing. Obviously this method cannot obtain the optimal yield because different bit-cells have its sensing latency respectively. This paper proposes a self-timed voltage-mode sense scheme named ST-VSS which can enable optimal timing depending on the bit-cell discharging ability. Two circuit structures are proposed: The single SA structure uses a multiplexer at the input of the SA. Its successive sensing operations are implemented with input offset flipping. A dual SA structure is reconfigured by built-in-self-test (BIST) method to the opposite offset states to monitor sensing results from each other. The sensing operation can be immediately terminated after successful reading. The proposed ST-VSS is applied to a 32bits/word MRAM using 28-nm CMOS process. Simulation results show that the successful sensing rate across a wide range of voltages can be improved, comparing with the conventional scheme. The single SA structure obtains 32%~42% yield improvement, costs 44.1%/26.9%/19.3% energy, and brings 8.3%/5.8%/2.9% layout area penalty in 128/256/512 column depth, respectively. The dual SA structure gets 54%~65% yield improvement, costs 66.2%/38.6%/27.5% energy, and brings 26.4%/13.8%/7.1% area penalty in 128/256/512 column depth conditions, respectively.