2019 · 24 citations · 9 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignVlsi DesignField-programmable Gate Array ArchitectureFpga ArchitectureLookup TablesLow-power Digital Circuit DesignLow-power Fpga DesignPower OptimizationAdder DesignAddersArea-efficient Fpga ArchitectureArithmetic Logic Unit ArchitectureCarry Chain ArchitectureCarry-save LogicLow-power AddersPower-aware Fpga Architecture
The paper presents a new and modified area and power efficient carry select adder is proposed using Weinberger architecture and it is compared for efficiency with modified Carry Select Adder using Han Carlson, Brent Krung, and Ling adder architectures along with conventional carry select adder. Carry Select Adder proposed here using Weinberger architecture turned out to be the best in terms of area and power. Simulations of all five adder architectures are performed in Xilinx Vivado tool version 14.4 and hardware implementations are performed on zynq 7000 FPGA board which uses 28nm technology.
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O. J. Bedrij · IRE Transactions on Electronic Computers · 1962 · 391 citations
Design of high speed hybrid carry select adder
Surendra S. Parmar, Kamaljit Singh · 2013 · 65 citations · Full text
Area efficient modified vedic multiplier
G. Challa Ram, Y. Rama Lakshmanna, K. Bala Sindhuri · 2016 · 62 citations