K. Bala Sindhuri

Area efficient modified vedic multiplier

G. Challa Ram, Y. Rama Lakshmanna, D. Sudha Rani et al. · 2016 · 62 citations

Array Computing, Engineering, Energy Efficiency +8

Design and implementation of 32-bit adders using various full adders

K. Anirudh Kumar Maurya, Y. Rama Lakshmanna, K. Bala Sindhuri et al. · 2017 Innovations in Power and Advanced Computing Technologies (i-PACT) · 2017 · 33 citations

Hardware Security, Engineering, Vlsi Design +9

Low power and area efficient Wallace tree multiplier using carry select adder with binary to excess-1 converter

R. Bala Sai Kesava, B. Lingeswara Rao, K. Bala Sindhuri et al. · 2016 · 32 citations

Low Power, Electrical Engineering, Wallace Tree Multiplier +14

Design of delay efficient modified 16 bit Wallace multiplier

G. Challa Ram, D. Sudha Rani, R. Balasaikesava et al. · 2016 · 29 citations

Electrical Engineering, Engineering, Vlsi Design +14

Implementation and comparison of VLSI architectures of 16 bit carry select adder using Brent Kung adder

N. Udaya Kumar, K. Bala Sindhuri, K. Durga Teja et al. · 2017 Innovations in Power and Advanced Computing Technologies (i-PACT) · 2017 · 24 citations

Hardware Security, High Speed Adder, Engineering +15