Carry-save Logic
Carry-Save Logic is a combinational logic technique used in arithmetic circuit design that belongs to the class of high-speed addition methods, distinguished by its ability to perform parallel addition of three or more binary numbers by separately computing sum and carry bits without immediate carry propagation, thereby reducing critical path delay in multi-operand addition.
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Publications
9.5K
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558
Authors
227
Institutions
Publications per year
2017–2026
24
261
Fast implementations of RSA cryptography
M. Shand, Jean Vuillemin · 2002 · 220 citations
Carry-select adder using single ripple-carry adder
T.-Y. Chang, Meng‐Jie Hsiao · Electronics Letters · 1998 · 206 citations
Efficient adder circuits based on a conservative reversible logic gate
J.W. Bruce, Mitchell A. Thornton, Lokesh Shivakumaraiah et al. · 2003 · 177 citations
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227
University of California, Los Angeles
Los Angeles, United States
13 h-index
31 publications
1.2K citations
Siemens (Germany)
Munich, Germany
6 h-index
12 publications
376 citations

Linköping University
Linköping, Sweden
5 h-index
12 publications
321 citations
École Polytechnique Fédérale de Lausanne
Lausanne, Switzerland
5 h-index
10 publications
371 citations
University of Patras
Pátrai, Greece
5 h-index
7 publications
426 citations

Universidad de Málaga
Málaga, Spain
4 h-index
8 publications
171 citations
The University of Texas at Austin
Austin, United States
4 h-index
9 publications
444 citations
Universidade de Santiago de Compostela
Santiago de Compostela, Spain
4 h-index
9 publications
184 citations
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35 publications · 2.3K citations
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12 publications · 706 citations
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10 publications · 479 citations
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6 publications · 181 citations
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6 publications · 299 citations
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