Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration

TLDR

Fan‑out wafer‑level packaging and panel‑level packaging are emerging microelectronics trends that enable high miniaturization and heterogeneous integration on increasingly large substrates, offering a pathway to lower cost and higher productivity. This study aims to develop an ASIC package with integrated surface‑mount capacitors using both FOWLP and PLP technologies. The authors employ FOWLP and PLP processes on a 200‑mm wafer, integrating SMD capacitors into the ASIC package while maintaining the same materials, equipment, and process flow. The approach proved successful on a 200‑mm wafer and was scaled to a 457 × 305 mm panel, demonstrating low‑cost, large‑area packaging capability.

Abstract

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12"/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.