Too Noisy at the Bottom? —Random Telegraph Noise (RTN) in Advanced Logic Devices and Circuits

Abstract

In this paper, the recent advances of our studies on RTN are presented from device, circuit, and EDA perspectives. RTN characteristics in FinFETs are investigated and compared with planar devices. The AC RTN effect is discussed for understanding RTN impacts in practical circuit applications. Then, a new and efficient circuit simulation platform for RTN is presented for the first time, which has been implemented in HSPICE using OMI/TMI. In addition, some open questions related to RTN are discussed with outlooks.