First Transistor Demonstration of Thermal Atomic Layer Etching: InGaAs FinFETs with sub-5 nm Fin-width Featuring in situ ALE-ALD

Abstract

For the first time, thermal atomic layer etching (ALE) on InGaAs-based III-V heterostructures is demonstrated. Also, we report the first transistors fabricated by the thermal ALE technique in any semiconductor system. We further highlight one unique advantage of thermal ALE: its integration with atomic layer deposition (ALD) in a single vacuum chamber. Using in situ ALE-ALD, we have fabricated the most aggressively scaled self-aligned In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As n-channel FinFETs to date, featuring sub-5 nm fin widths. The narrowest FinFET with Wf=2.5 nm and Lg = 60 nm shows gm=0.85 mS/μm at Vds=0.5 V. Devices with Wf=18 nm and Lg=60 nm demonstrate gm=1.9 mS/μm at Vds=0.5 V. Subthreshold swings averaging Slin=70 mV/dec and Ssat=74 mV/dec across the entire range of W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> , at minimum Lg=60 nm have been obtained. These are all record results. The transistors demonstrated here show an average 60% gm improvement over devices fabricated through conventional techniques. These results suggest a very high-quality MOS interface obtained by the in situ ALE-ALD process.