Gate architecture design for enhancement mode p-GaN gate HEMTs for 200 and 650V applications

Abstract

Enhancement mode p-GaN gate HEMTs with two different gate architectures are compared. The gate is realized by stacked (1-mask) or separate patterning (3-mask) of the p-GaN and gate metal layers. The 3-mask gate architecture, in this work implemented with a novel TiN interlayer, offers the advantage of a low gate resistance, increased flexibility in field plate design and reduced dynamic RDS-ON at high VDS. Both for 200 and 650 V applications excellent device performance is demonstrated on 200 mm substrates using Au-free processing, with a threshold voltage of well above 2 V and a dynamic R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS-ON</sub> of below 20%. The 650 V rated device, with a hard breakdown voltage of 1000 V, passes the wafer level HTRB test at 150 °C.