Influence of Deposition Temperature and Source Gas in PE-CVD for SiO₂ Passivation on Performance and Reliability of In–Ga–Zn–O Thin-Film Transistors

Abstract

In this paper, we investigated the influence of both source gas and deposition temperature in plasma-enhanced chemical vapor deposition (PE-CVD) for a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> passivation layer on the electrical properties and reliability of a bottom-gate In-Ga-Zn-O thin-film transistor (IGZO TFT). Two gas chemistries consisting of SiH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> -N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O-N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and tetraethoxysilane (TEOS)-O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> were utilized as the source gases for the PE-CVD SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> deposition, and the deposition temperature (TD) was adjusted from 180 °C to 380 °C. The TFT properties were basically identical for both gas chemistries at TD of 180 °C. When TD increased to 300 °C or higher, the TFTs with the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> passivation deposited by SiH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> -N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O-N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gas chemistry (SiH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> -SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) drastically changed from the transistor to the conductor. In contrast, the TFT with TEOS-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> passivation maintained its TFT characteristics even at TD of 380 °C, despite the degradation of subthreshold characteristics and a negative shift of turn-on voltage were observed due to an electron injection barrier lowering as TD increased to 310 °C or higher. We also revealed that a stacked SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> passivation that is deposited at a different TD is an effective technique to improve the performance and reliability of the IGZO TFT.