Process technology for IBM 14-nm processor designs featuring silicon-on-insulator FinFETs

Abstract

A highly optimized silicon-on-insulator FinFET technology is utilized for the IBM processor designs in the 14-nm node. This process technology has a number of unique elements that enable these product designs—namely, deep-trench embedded dynamic random access memory, multiple work-function FinFET devices, and a hierarchical 17-level metal back end of line. In this paper, we highlight these key features and provide a general background for the technology used to make these very large (∼700 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mm</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ), complex chips operating at peak frequencies in excess of 5 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GHz</i> , and we discuss specific technical challenges.