A 140 MHz 1 Mbit 2T1C gain-cell memory with 60-nm indium-gallium-zinc oxide transistor embedded into 65-nm CMOS logic process technology

Abstract

An embedded 1 Mbit 2T1C gain-cell memory macro using indium-gallium-zinc oxide semiconductor FETs (OSFETs) with an extremely low off-state current of less than 1 zA (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-21</sup> A) was fabricated. In the 2T1C gain cell, an OSFET for the write operation was stacked over a SiFET for the read operation. The 1 Mbit macro was fabricated using a combination of 60-nm OSFET and 65-nm CMOS processes. It achieves a 140 MHz operation and data retention of more than 1 h. Its static power in the standby state and active power are 31 μW and 64 μW/MHz, respectively. The macro with long-term data retention can reduce the static power by power gating. 2T1C OSFET-based embedded memory is applicable to devices requiring high performance as well as low power.