Performance analysis of a SiC MOSFET half bridge power module with a Miller clamp

Abstract

This paper presents a comparison of Miller clamp implementations for a high-performance SiC MOSFET half-bridge power module. The objective of this work is to demonstrate the optimal location and layout of a Miller clamp to minimize false turn-on behavior under very high-speed switching. Utilization of a Miller clamp exhibits benefits over a standard gate driver configuration, but due to its physical location, it cannot provide optimal clamping. In this paper a novel approach is taken by integrating the Miller clamp inside a SiC half bridge power module. The close physical location of the Miller clamp to the SiC MOSFETs provides the best possible gate control under high-speed switching events and completely eliminates unwanted Miller induced turn-on.