6.4 A 64Gb/s PAM-4 transmitter with 4-Tap FFE and 2.26pJ/b energy efficiency in 28nm CMOS FDSOI

Abstract

Electrical link migration requires serial interfaces to operate at increasing data rates. Despite the fact that most standards still employ NRZ, practical signal integrity constraints demand PAM-4 modulation, especially for some interconnect applications and low-loss profiles [1]. Nevertheless, compared to NRZ, the design of high-speed PAM-4 transmitters entails several challenges. Achieving high linearity without reducing the output amplitude is key to preserve high SNR, which is tightened by the intrinsic 1/3 eye amplitude reduction. Moreover, transitions between non-adjacent levels reduce horizontal eye openings, demanding wide bandwidth and tight timing constraints. In light of the above issues, pushing the transmitter to high data-rates while maintaining signal integrity and energy efficiency is challenging. In fact, published PAM-4 transmitters [2–5] do not meet the CEI-56G-PAM4 standard [1], requiring up to 56Gb/s and 4-taps of feedforward equalization (FFE). To reach the target, improvements on both the architecture and the circuit side are required. A serializer architecture is presented in this paper. To save power, clocking signals are generated and distributed at quarter-rate, but the last stage employs 2∶1 multiplexers (MUXs) driven by half-rate clocks generated locally to overcome the speed limitation of 4∶1 MUXs. Moreover, a new current-mode driver allows high swing and good linearity by raising the power supply without compromising speed and reliability, and a double T-coil splits transistors and ESD parasitics to meet the bandwidth requirements for the target data rate.