Simone Erba - Concepedia

Author

Simone Erba

University of Pavia

Also Known As

S. Erba, Simone Erba

Publications

404

Citations

H-Index

Concepts

All Affiliations

University of Pavia STMicroelectronics (Italy)University of Modena and Reggio Emilia

About

Simone Erba is an author at University of Pavia specializing in computer engineering, engineering, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	9	9	370
2	Computer Engineering	9	9	370
3	Electrical Engineering	7	7	281
4	Systems Engineering	1	1	41
5	Computer Architecture	1	1	46

Simone Erba

Publications

370

Citations

H-Index

Page 1

	Year	Citations
A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS Emanuele Depaoli, Hongyang Zhang, Marco Mazzini, IEEE Journal of Solid-State Circuits Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignMixed-signal Integrated Circuit	2018	70
A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI Matteo Bassi, Francesco Radice, Melchiorre Bruccoleri, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineeringVlsi DesignNm Cmos FdsoiFull Swing	2016	50
A 2–11 GHz 7-Bit High-Linearity Phase Rotator Based on Wideband Injection-Locking Multi-Phase Generation for High-Speed Serial Links in 28-nm CMOS FDSOI Enrico Monaco, Gabriele Anzalone, Guido Albasini, IEEE Journal of Solid-State Circuits Electrical EngineeringEngineering28-Nm Cmos FdsoiPhase RotatorsQuadrature Error	2017	50
A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication Massimo Pozzoni, Simone Erba, P. Viola, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignClock RecoverySsc Tolerant CdrNm Cmos	2009	46
6.4 A 64Gb/s PAM-4 transmitter with 4-Tap FFE and 2.26pJ/b energy efficiency in 28nm CMOS FDSOI Giovanni Steffan, Emanuele Depaoli, Enrico Monaco, Electrical EngineeringCmos FdsoiEngineeringEnergy EfficiencyPam-4 Transmitter	2017	46
A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS Emanuele Depaoli, Enrico Monaco, Giovanni Steffan, Multi-carrier CommunicationEngineeringVlsi DesignLow-power TransceiversFdsoi Cmos	2018	43
3.6 A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI Matteo Bassi, Francesco Radice, Melchiorre Bruccoleri, Hardware SecurityElectrical EngineeringCmos FdsoiEngineeringPam-4 Transmitter	2016	41
A multi standard 1.5 to 10Gb/s latch-based 3-tap DFE receiver with a SSC tolerant CDR for serial backplane communication Massimo Pozzoni, Simone Erba, P. Viola, EngineeringVlsi DesignSsc Tolerant CdrNm CmosIntegrated Circuits	2008	12
A 25mW Highly Linear Continuous-Time FIR Equalizer for 25Gb/s Serial Links in 28-nm CMOS Fabrizio Loi, Enrico Mammei, Simone Erba, IEEE Transactions on Circuits and Systems I Regular Papers 25-Gb/s Fir EqualizerElectrical EngineeringEngineeringSerial LinksMixed-signal Integrated Circuit	2017	12

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