A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication

Abstract

This paper presents a 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS. The multiple constraints set by industry standards ask for a receiver architecture capable of simultaneously addressing channel loss impairments, high frequency-difference tracking and low serial to parallel latency. An adaptive 3-tap DFE data recovery is based on a direct-feedback topology to provide a continuous equalized signal assuring a robust clock-data self alignment. A latch-based DFE topology has been developed to overcome the classical DFE feedback loop-delay issue. A digital early-late clock recovery has been proven for plusmn5000 ppm SSC tracking. Extensive digital features allow self-calibration and internal eye analysis. The device, realized in a 65 nm technology, supports more than 36" FR4 at 6 Gb/s with SSC and 28" at 8.5 Gb/s while keeping 0.4 UI of additional sinusoidal jitter tolerance, consuming 140 mW from 1V.