Daniele Baldi

A Low-Noise Design Technique for High-Speed CMOS Optical Receivers

Dan Li, Gabriele Minoia, Matteo Repossi et al. · IEEE Journal of Solid-State Circuits · 2014 · 156 citations

Alternative Topologies, Photonics, Engineering +12

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi et al. · IEEE Journal of Solid-State Circuits · 2010 · 116 citations

Ghz Wideband Adpll, Fractional Spurs, Clock Recovery +8

A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques

Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi et al. · IEEE Journal of Solid-State Circuits · 2009 · 102 citations

Analog-to-digital Converter, High-frequency Device, Data Converter +7

A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction

Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi et al. · 2008 · 46 citations

Resolution Tdc, High-frequency Device, Clock Recovery +10

A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication

Massimo Pozzoni, Simone Erba, P. Viola et al. · IEEE Journal of Solid-State Circuits · 2009 · 46 citations

Engineering, Vlsi Design, Clock Recovery +11