Colin Weltin-Wu

An Event-driven Clockless Level-Crossing ADC With Signal-Dependent Adaptive Resolution

Colin Weltin-Wu, Y. Tsividis · IEEE Journal of Solid-State Circuits · 2013 · 138 citations

Adaptive Resolution, Engineering, Clock Recovery +11

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi et al. · IEEE Journal of Solid-State Circuits · 2010 · 116 citations

Ghz Wideband Adpll, Fractional Spurs, Clock Recovery +8

A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques

Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi et al. · IEEE Journal of Solid-State Circuits · 2009 · 102 citations

Analog-to-digital Converter, High-frequency Device, Data Converter +7

A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction

Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi et al. · 2008 · 46 citations

Resolution Tdc, High-frequency Device, Clock Recovery +10

Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement

Ian Galton, Colin Weltin-Wu · IEEE Transactions on Circuits and Systems I Regular Papers · 2018 · 45 citations

Engineering, Phase Error, Oscillators +18