Colin Weltin-Wu

An Event-driven Clockless Level-Crossing ADC With Signal-Dependent Adaptive Resolution

Colin Weltin-Wu, Y. Tsividis · IEEE Journal of Solid-State Circuits · 2013 · 145 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation

Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi et al. · IEEE Journal of Solid-State Circuits · 2010 · 118 citations

Engineering, Electrical Engineering, Analog Electronics +14

A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques

Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi et al. · IEEE Journal of Solid-State Circuits · 2009 · 103 citations

Engineering, Electrical Engineering, Analog Electronics +16

Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement

Ian Galton, Colin Weltin-Wu · IEEE Transactions on Circuits and Systems I Regular Papers · 2018 · 48 citations

Engineering, Electrical Engineering, Circuit Theory +16

A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction

Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi et al. · 2008 · 46 citations

Engineering, Electrical Engineering, Analog Electronics +14