3.6 A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI

Abstract

The development of next-generation electrical link technology to support 400Gb/s standards is underway [1-5]. Physical constraints paired to the small area available to dissipate heat, impose limits to the maximum number of serial interfaces and therefore their minimum speed. As such, aggregation of currently available 25Gb/s systems is not an option, and the migration path requires serial interfaces to operate at increased rates. According to CEI-56G and IEEE P802.3bs emerging standards, PAM-4 signaling paired to forward error correction (FEC) schemes is enabling several interconnect applications and low-loss profiles [1]. Since the amplitude of each eye is reduced by a factor of 3, while noise power is only halved, a high transmitter (TX) output amplitude is key to preserve high SNR. However, compared to NRZ, the design of a PAM-4 TX is challenged by tight linearity constraints, required to minimize the amplitude distortion among the 4 levels [1]. In principle, current-mode (CM) drivers can deliver a differential peak-to-peak swing up to 4/3(VDD-VOV), but they struggle to generate high-swing PAM-4 levels with the required linearity. This is confirmed by recently published CM PAM-4 drivers, showing limited output swings even with VDD raised to 1.5V [2-4]. Source-series terminated (SST) drivers naturally feature better linearity and represent a valid alternative, but the maximum differential peak-to-peak swing is bounded to VDD only. In [5], a dual-mode SST driver supporting NRZ/PAM-4 was presented, but without FFE for PAM-4 mode. In this paper, we present a PAM-4 transmitter leveraging a hybrid combination of SST and CM driver. The CM part enhances the output swing by 30% beyond the theoretical limit of a conventional SST implementation, while being calibrated to maintain the desired linearity level. A 5b 4-tap FIR filter, where equalization tuning can be controlled independently from output matching, is also embedded. The transmitter, implemented in 28nm CMOS FDSOI, incorporates a half-rate serializer, duty-cycle correction (DCC), ≫2kV HBM ESD diodes, and delivers a full swing of 1.3V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ppd</sub> at 45Gb/s while drawing 120mA from a 1V supply. The power efficiency is ~2 times better than those compared in this paper.