A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With $≪ -$16 dB Return Loss Over 10 GHz Bandwidth

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is presented. The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 Gb/s. A thin-oxide pre-driver stage running at 1.0 V drives 22 parallel connected thick-oxide SST output stages operated at 1.5 V that feature a 5-bit 2-tap FIR filter whose adaptation is independent of the impedance tuning. To achieve a return loss of <formula formulatype="inline"><tex Notation="TeX">$≪-$</tex> </formula>16 dB up to 10 GHz a 40 <formula formulatype="inline"><tex Notation="TeX">$\mu$</tex> </formula>m<formula formulatype="inline"><tex Notation="TeX">$\,\times\,$</tex> </formula>40 <formula formulatype="inline"><tex Notation="TeX">$\mu$</tex> </formula>m T-coil complements the transmitter output. This half-bit-rate clock SST transmitter has a duty-cycle restoration capability of 5x, and the common-mode voltage noise is below 10 mV rms for high-, mid- and low-level terminations. The chip consumes 96 mW at 8.5 Gb/s and occupies 180 <formula formulatype="inline"><tex Notation="TeX">$\mu$</tex></formula>m <formula formulatype="inline"> <tex Notation="TeX">$\times\, \hbox{360}\ \mu$</tex></formula>m. In addition to the transmitter design, guidelines for the T-coil design are presented. </para>