Detailed SET Measurement and Characterization of a 65 nm Bulk Technology

Abstract

Single Event Transients (SETs) are a major concern for space applications, particularly when hardened flip flops are used to reduce the sensitivity of sequential logic. Characterizing SETs is complex as both the cross section and the pulse width must be measured. In the 65 nm test chip presented in this paper, three different SET measurement circuits, implemented on the same die, are characterized and compared. Using these SET detectors, heavy-ion test results are presented. The detectors are compared and a detailed study of the SET sensitivity of multiple gates operating at different logical, load and voltage conditions is presented.