IEEE Transactions on Circuits & Systems II Express Briefs · 2016 · 167 citations · 19 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignReconfigurable ComputingHardware AccelerationLow-power Digital Circuit DesignPower OptimizationAdder DesignArea-delay OptimizationLow-power AddersLow-power Reconfigurable DesignPower ConsumptionPower Consumption OptimizationPower-efficient Reconfigurable Design
In this brief, we propose a fast yet energy-efficient reconfigurable approximate carry look-ahead adder (RAP-CLA). This adder has the ability of switching between the approximate and exact operating modes making it suitable for both error-resilient and exact applications. The structure, which is more area and power efficient than state-of-the-art reconfigurable approximate adders, is achieved by some modifications to the conventional carry look ahead adder (CLA). The efficacy of the proposed RAP-CLA adder is evaluated by comparing its characteristics to those of two state-of-the-art reconfigurable approximate adders as well as the conventional (exact) CLA in a 15 nm FinFET technology. The results reveal that, in the approximate operating mode, the proposed 32-bit adder provides up to 55% and 28% delay and power reductions compared to those of the exact CLA, respectively, at the cost of up to 35.16% error rate. It also provides up to 49% and 19% lower delay and power consumption, respectively, compared to other approximate adders considered in this brief. Finally, the effectiveness of the proposed adder on two image processing applications of smoothing and sharpening is demonstrated.
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Hamid Reza Mahdiani, Ali-Akbar Ahmadi, S.M. Fakhraie et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2010 · 605 citations
Ning Zhu, Wang Ling Goh, W ZHANG et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009 · 377 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +15