Hamid Reza Mahdiani - Concepedia

Author

Hamid Reza Mahdiani

University of Tehran ORCID

Also Known As

H R Mahdiani, H. R. Mahdiani, H.R. Mahdiani, Hamid Reza Mahdiani, Mahdiani, Hamid Reza

Publications

815

Citations

H-Index

Concepts

All Affiliations

University of Tehran Shahid Beheshti University

About

Hamid Reza Mahdiani is an author at University of Tehran specializing in computer architecture, engineering, and computer engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	6	6	738
2	Computer Engineering	6	6	738
3	Computer Science	6	6	738
4	Systems Engineering	3	3	627
5	Electrical Engineering	1	1	62

Hamid Reza Mahdiani

Publications

750

Citations

H-Index

Page 1

	Year	Citations
Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications Hamid Reza Mahdiani, Ali-Akbar Ahmadi, S.M. Fakhraie, IEEE Transactions on Circuits and Systems I Regular Papers EngineeringVlsi DesignEvolvable HardwareBiometricsHardware Algorithm	2010	592
Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors Hamid Reza Mahdiani, S.M. Fakhraie, C. Lucas IEEE Transactions on Neural Networks and Learning Systems EngineeringMachine LearningComputer ArchitectureLarge Scale IntegrationHardware Security	2012	62
Defuzzification block: New algorithms, and efficient hardware and software implementation issues Hamid Reza Mahdiani, A. Banaiyan, Mohammad Haji Seyed Javadi, Engineering Applications of Artificial Intelligence Hardware SecurityEngineeringComputer EngineeringComputer ArchitectureParallel Programming	2012	28
Small Constant Mean-Error Imprecise Adder/Multiplier for Efficient VLSI Implementation of MAC-Based Applications Mohammad Haji Seyed Javadi, Mohammad Hossein Yalame, Hamid Reza Mahdiani IEEE Transactions on Computers EngineeringVlsi DesignComputer ArchitectureImprecise Computational BlocksHardware Security	2020	21
Cost-Performance Co-Analysis in VLSI Implementation of Existing and New Defuzzification Methods A. Banaiyan, S.M. Fakhraie, Hamid Reza Mahdiani EngineeringCost-performance Co-analysisComputer ArchitectureSoftware EngineeringVlsi Implementation	2006	18
A High-Performance Scalable Shared-Memory SVD Processor Architecture Based on Jacobi Algorithm and Batcher’s Sorting Network Seyed Mohammad Reza Shahshahani, Hamid Reza Mahdiani IEEE Transactions on Circuits and Systems I Regular Papers Inherent ParallelismEngineeringComputer ArchitectureJacobi SvdVector Processing	2020	17
FiCA: A Fixed-Point Custom Architecture FastICA for Real-Time and Latency-Sensitive Applications Seyed Mohammad Reza Shahshahani, Hamid Reza Mahdiani IEEE Transactions on Neural Systems and Rehabilitation Engineering	2022	12

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