2006 · 11 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSystem-on-chip DesignAnalog Integrated CircuitsBuilt-in Self-testDesign For TestabilityDigital Signal ProcessingLow-noise Circuit DesignMixed-signal Integrated Circuit DesignAnalog Circuit DesignAnalog TestabilityBuilt-in Self-test For Analog CircuitsHardware Overhead AnalysisHistogram AnalysisMixed-signal Built-in Self-testMixed-signal TestMixed-signal Testability
A low-cost BIST scheme based on linear histogram for testing ADC is presented in this paper. A parallel time decomposition technique is presented to minimize not only hardware overhead but also testing time of the BIST scheme based on histogram. An area-efficient linear triangular waveform generator is discussed as test stimulus. The technique uses digital delta-sigma noise shaping to generate the on-chip precise analog stimulus and simplify the analog circuit of the generator at same time. A practical implementation is described and the performance is evaluated.
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