IEEE Journal of Solid-State Circuits · 2003 · 146 citations · 18 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSystem-on-chip DesignAnalog Integrated CircuitsAnalog IntegrationBuilt-in Self-testMixed-signal Integrated Circuit DesignMixed-signal IntegrationMixed-signal ModelingAccuracyAnalog Built-in Self-testAnalog Circuit DesignAnalog TestabilityBuilt-in Self-test For Analog CircuitsCalibration Techniques For Analog CircuitsMixed-signal TestMixed-signal Testability
The paper proposes a practical on‑chip method for generating precise, slow analog ramps to support time‑domain testing, monotonicity checks, and histogram‑based ADC evaluations. The method employs an analog discrete‑time adaptive calibration scheme, achieving a minimum slope of 0.4 V/ms, and offers three implementations varying in accuracy and complexity. Measurements confirm high accuracy and programmability, with slope error below 0.6 % and integral nonlinearity within ±175 µV, and experimental data match theoretical predictions.
A practical approach to generate on-chip precise and slow analog ramps, intended for time-domain analog testing, monotonicity and histogram-based tests of ADCs is proposed. The technique uses an analog discrete-time adaptive scheme to calibrate the ramp generator. The lowest slope is 0.4V/ms. Three implementations are presented for different levels of accuracy and complexity. Measurement results show excellent accuracy and programmability, up to only 0.6% of slope error and maximum integral nonlinearity error of ±175μV. Experimental and theoretical results are in good agreement.
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