Effect of pMOST bias-temperature instability on circuit reliability performance

Abstract

This work investigated the impact of pMOST bias-temperature (BT) degradation on logic product speed (F/sub max/) and minimum allowed operating voltage (V/sub ccmin/). Fluorine implants after poly etch and before hard-mask removal are utilized to separate out the BT instability effects from other reliability degradations. Physical mechanisms and models are proposed to explain the interaction of fluorine with device and circuit reliability. A reliability guardband in F/sub max/ and V/sub ccmin/ is recommended as part of the production testing to ensure reliable logic product performance and functionality during the product's lifetime.