6um Pitch High Density Cu-Cu Bonding for 3D IC Stacking

Abstract

For ultra-fine pitch and high density Cu pillar low temperature bonding (200°C), the surface contact between substrate and Cu pillar array is the key. Therefore, the fabrication quality of copper bump array affects severely the bonding results. The qualitative factors include (1) Cu pillar array height uniformity, (2) free of copper oxide layer, (3) Cu material property (e.g. elastic modulus, grain size), (4) certain levels of roughness and (5) even the Cu pillar with or without TSV in the wafer. In this paper, test vehicle with dia3um and pitch 6um TSV 20um thin wafer are design and fabricated. The test vehicle is used to study above major bonding contributors. Solid Cu-Cu interconnects are demonstrated with both Chip to chip (C2C) and Chip to wafer (C2W) process. The developed process is promising for high density I/O (<;10um pitch) low temperature (200°C) Cu-Cu bonding for 3D stacking.