Accumulation mode triple gate SOI LDMOS with ultralow on-resistance and enhanced transconductance

Abstract

An accumulation mode triple gate (ATG) SOI LDMOS is proposed and its mechanism is investigated and analyzed. The proposed ATG SOI LDMOS features a three dimensional triple gate consisted of a planar gate and surrounding trench gates. The trench gate embeds into the drift region with slant oxide isolation. The triple gate of the proposed device enlarges the channel width and improves the transconductance. In the on-state, an electron accumulation layer is formed at the drift region along the sidewall of the trench gate and provides an ultralow resistance current path, which dramatically decreases the specific on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ). In the off-state, the extended trench gate modulates the electric field distribution as a slant field plate role and assists depleting the N-drift region, and hence increases the N-drift doping concentration to further decrease the R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> . Compared with conventional SOI LDMOS and Superjunction SOI LDMOS, the ATG SOI LDMOS reduces R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> the by 73% and 57%, respectively. Moreover, the proposed device obtains higher transconductance value and better immunity to the variation of the drift doping concentration.