Interface Layers for High-k/Ge Gate Stacks: Are They Necessary?

Abstract

We discuss the effects of interface layers between high-k gate insulators and the Ge substrate on the electrical characteristics of Ge MOS devices. Our work has focused on both germanium oxynitride (GeO x N y ) and tantalum oxynitride (TaO x N y ) interface layers. We find that ultrathin interface layers of TaO x N y , a high permittivity diffusion barrier, produce greatly improved charge trapping characteristics and promising capacitance scaling for high-k/Ge gate stacks. Effects of interface layers on interface state density and the frequency dispersion of the capacitance-voltage (CV) behavior under inversion are also described.